1. Field of the Invention
The present invention relates to electronic digital processing systems and, more particularly, to data processing systems which employ virtual memory addressing. More particularly, the present invention is directed to a method for reducing operating system overhead caused by translation look aside buffer purging.
2. Description of the Prior Art
Computer systems implement virtual memory systems to more effectively manage real computer memory for computer tasks. Virtual memory is typically organized as a series of memory pages of fixed size, for example, 4096 bytes. Memory pages in turn, are grouped into segments. A virtual memory address comprises three fields as shown in FIG. 1. The segment index 100 is used to access a segment table to determine the real location of a segment containing several pages. Page index 102 is an index to access a particular page within that segment, and offset 104 provides the location of data within that particular page.
During task processing virtual addresses must be translated to real addresses for memory access to occur. Virtual to real address translation is carried out by a dynamic address translation mechanism 202 as shown in FIG. 2. Dynamic address translation typically requires two memory accesses: to the segment table and to the page table, before the real address can be calculated and the memory accessed for data. The result of dynamic address translation is a real address that can be used by the processor to access real memory.
Performing dynamic address translation for every virtual memory access greatly increases processing overhead. It is highly desirable to reduce the number of memory accesses and instruction path length required for address translation. Computer system designers have made the address resolution process more efficient by introducing a translation look aside buffer (TLB). A translation look aside buffer (208 in FIG. 2) typically contains a fixed number of entries, e.g. 256. Each TLB entry provides a direct translation from a virtual address to a real address. A typical TLB entry is shown in FIG. 3. The first field 230 is the segment table origin (STO) indicating the origin of the allocated segment table. Virtual address 232 contains the segment index (sx), page index (px), and offset (bx) as shown in FIG. 1. Real address 234 contains the real memory address used for accessing the data.
In operation, the processor initially performs dynamic address translation to determine the real address for a particular virtual address. The resolved entry is then added to the translation look aside buffer (TLB) 208. When future address resolution requests are made, the TLB is first checked to determine whether or not it contains an entry resolving that particular virtual address. If the virtual address is not already in the TLB, then dynamic address translation must be performed and a new TLB entry created and added to the TLB possibly casting out an older entry.
The TLB entries are only valid for translations within a particular segment table. Different segment tables may result in different virtual to real conversions. Without a mechanism to differentiate between TLB entries of different segment tables, the TLB must be purged at every task dispatch to prevent invalid address translations. Typically, the segment table origin is maintained in the TLB to associate a virtual to real conversion with the appropriate segment table.
A segment table origin (STO) defines an address space. An address space will typically persist through one or more dispatches. Each time the address space is dispatched, the TLB may have some entries left over from the previous execution of the address space which will improve performance since the initial address translation is not required. Eventually the use of address space will terminate, though it may later be reused. The virtual to real translations in the TLB will not be valid for subsequent uses of the address space.
At each address space dispatch, the contents of the TLB may or may not be valid, depending on whether the address space has been reused since the last time it was dispatched.
The processing overhead cost to purge the TLB is determined by comparing the time to purge to the length of tasks running on the computer system. The overhead to purge the TLB before task initiation is insignificant for very long running tasks. However, for a very short running task, the purge TLB overhead may constitute a significant portion of the task operating elapsed time. Thus, the requirement to frequently purge TLB adds undesired overhead to the system and reduces processor throughput. This penalty is particularly severe in short task, transaction processing systems.
Various methods have been suggested to reduce the need to purge the translation look aside buffer. U.S. Pat. No. 4,525,778 to Cane suggests the use of tag bits and a process identifier with each TLB entry. An address resolution access to the TLB must compare the tag bits and process identifier to determine whether this TLB entry is valid for the accessing process. If not, the entry is invalidated. Other such systems have been proposed to add marking bits to the TLB which are then compared upon TLB access.
The use of additional bits to mark each TLB entry adds logic overhead to the processing system. It would be desirable to avoid adding hardware or software to set and test the additional flags. It is therefore desirable to develop a TLB management system that reduces the instance of translation look aside buffer purges without adding hardware to the TLB accessing circuit.
The technical problem that must be resolved is to provide a system that minimizes TLB while assuring that address resolution accesses to always result in valid addresses.